1. Field of the Invention
The present invention relates, in general, to capacitor structures, and, more particularly, to filter capacitor structures for monolithically integrated circuits.
2. Relevant Background
On large integrated circuits (ICs) it is necessary to route the direct current (DC) power buses to all the circuits on the IC requiring power. The DC power bus system distributes positive and/or negative power throughout the IC. Typically one of the polarities is ground and the other is designated as V.sub.CC or V.sub.DD. The DC power distribution system provides low resistance paths between the power supply nodes and each circuit being powered. Voltage drops along the power distribution bus should not affect other circuits being powered from the same bus, even during high current loads.
Power is supplied to circuitry formed on an IC from, for example, an external power supply coupled to wire bonding pads. Alternatively, many ICs provide an on-chip voltage regulator to decrease a higher voltage (e.g., 5.OV) provided by an external power supply to a lower voltage (e.g., 3.3V) required by the internal circuitry on the IC. To limit undesirable voltage ripple on the internal voltage supply node, the time constant of the regulator is desirably much longer than the internal cycle of the device. This prevents undesired voltage ripple within a cycle that can upset analog voltage levels. A filter capacitor is coupled across the power supply wire bonding pads (or the on-chip voltage regulator output nodes) to help smooth voltage fluctuations at the power and ground nodes on the IC and fluctuations caused by the external power supply.
In practice, filter capacitors consume a great deal of chip area without adding functionality other than the aforementioned filtering function. In general, cost and chip size considerations dictate limiting the filter capacitor to modest sizes. One strategy for providing a large filter capacitance is to dice the filter capacitor into pieces and distribute the pieces throughout the IC chip in areas that are not used for circuitry. The diced pieces are then coupled in parallel to form the requisite, relatively large capacitance.
Some conventional DC power distribution bus layouts use a single large bus that is branched repeatedly to attempt to reach every element to be powered. However, because of the difficulty inherent in crossing one conductor over another, it is often not possible to guarantee that all circuits can be powered unless multiple metal layers are used. Additional metal layers increase chip cost significantly. Also, the branching structure of the buses causes high currents to flow in some portions and could cause voltage sagging and undesired circuit interaction. Moreover, such relatively high resistance power distribution buses dissipate energy as heat that must be removed from the IC package. Heat removal limits device performance and functionality and makes the IC larger and thus more expensive, as well as making the packaging more expensive.
"Multi-tier", "grid" or "mesh" power distribution buses comprise a plurality of power conductors that are coupled to a common power supply or ground node. The power conductors are typically arranged parallel to each other and extend in one direction across the integrated circuit. Metal straps running perpendicular to the power conductors are used to couple each tier of the power conductors together in a grid fashion. These perpendicular straps are generally laid out to be relatively wide to provide low resistance connections. Also, the perpendicular straps must be placed frequently along the length of the power conductors to effectively reduce sagging of the voltage on the power conductors.
In addition to power distribution buses, ICs typically include signal buses for distribution of data and control signals about the IC. A gridded power distribution bus requires that the signal buses traverse the power distribution buses at many locations. When metal straps are used, the parasitic capacitance between the signal buses and the power distribution buses is relatively high because there is only relatively thin insulation between the signal buses and the metal straps. This high parasitic capacitance reduces the maximum signal frequency on the signal buses thereby reducing speed and functionality of the IC.
An example of high current demand circuits are sense amplifiers in a dynamic random access memory (DRAM). In a typical DRAM circuit, one sense amplifier is supplied for each bit line pair in the device. For each sense amplifier, the standby (i.e., non-switching) state requires relatively little current. When activated, however, each sense amplifier may draw more than 1000 times its standby current. Moreover, state of the art DRAM devices may have more than 1000 sense amplifiers activated simultaneously, resulting in very high current draw on the regulator. During high current demand, regulation can become poor and the chip's internal voltage levels can drop or "sag" significantly if the power distribution bus exhibits high resistance.
Capacitor structures used to implement a filter capacitor are desirably volumetrically efficient. In other words, the capacitor structure should have a high capacitance per unit volume ratio. Hence, the structures and processes used to implement capacitors are desirably compatible with a thin capacitor dielectric and allow topographically complex (i.e., non-planar or folded) capacitor plates to increase unit capacitance.